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mosel vitelic 1 V58C365164S 64 mbit ddr sdram 4m x 16, 3.3volt V58C365164S rev. 1.7 march 2002 preliminary 36 4 5 system frequency (f ck ) 275 mhz 250 mhz 200 mhz clock cycle time (t ck3 ) 3.6 ns 4 ns 5 ns clock cycle time (t ck2.5 ) 4.3ns 4.8 ns 6 ns clock cycle time (t ck2 ) 5.4ns 6 ns 7.5 ns features 4 banks x 1mbit x 16 organization high speed data transfer rates with system frequency up to 275 mhz data mask for write control (dm) four banks controlled by ba0 & ba1 programmable cas latency: 2, 2.5, 3 programmable wrap sequence: sequential or interleave programmable burst length: 2, 4, 8 for sequential type 2, 4, 8 for interleave type automatic and controlled precharge command suspend mode and power down mode auto refresh and self refresh refresh interval: 4096 cycles/64 ms available in 66-pin 400 mil tsop-ii sstl-2 compatible i/os double data rate (ddr) bidirectional data strobe (dqs) for input and output data, active on both edges on-chip dll aligns dq and dqs transitions with clk transitions differential clock inputs clk and clk power supply 3.3v 0.3v vddq (i/o) power supply 2.5 + 0.2v description the V58C365164S is a four bank ddr dram organized as 4 banks x 1mbit x 16. the V58C365164S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock all of the control, address, circuits are synchro- nized with the positive edge of an externally sup- plied clock. i/o transactions are possible on both edges of dqs. operating the four memory banks in an inter- leaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapless data rate is pos- sible depending on burst length, cas latency and speed grade of the device. device usage chart operating temperature range package outline clk cycle time (ns) power temperature mark jedec 66 tsop ii -36 -4 -5 std. l 0c to 70c blank
2 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S 66 pin plastic tsop-ii pin configuration top view pin names 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq 0 v ddq dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 v ssq v ddq v ssq nc v ddq ldqs nc v dd nc ldm we cas ras cs nc ba0 ba1 v ss dq 15 v ssq dq 14 dq 13 v ddq v ssq dq 10 dq 9 v ddq dq 8 nc dq 12 dq 11 v ssq udq s nc v ref v ss udm clk clk cke nc nc a11 a9 a 10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss 64m ddr sdram clk, clk differential clock input cke clock enable cs chip select ras row address strobe cas column address strobe we write enable udqs, ldqs data strobe (bidirectional) a 0 ?a 11 address inputs ba0, ba1 bank select dq 0 ?dq 15 data input/output udm, ldm data mask v dd power (+3.3v) v ss ground v ddq power for i/o?s (+2.5v) v ssq ground for i/o?s nc not connected v ref reference voltage for inputs v 58 c 3 6516 4 s a t xx ddrsdram cmos 3.3v vdd 4mx16, 4k refresh 4 banks component rev level component package, t = tsop sstl speed 36 (275mhz@cl3) mosel vitelic manufactured 4 (250mhz@cl3) 5 (200mhz@cl3) 2.5v vddq
mosel vitelic V58C365164S 3 V58C365164S rev. 1.7 march 2002 capacitance* t a = 0 to 70 c, v cc = 3.3 v 0.2 v, f = 1 mhz * note: capacitance is sampled and not 100% tested. absolute maximum ratings* operating temperature range ..................0 to 70 c storage temperature range ................-55 to 150 c input/output voltage.................. -0.3 to (v cc +0.3) v power supply voltage .......................... -0.3 to 4.6 v power dissipation ...........................................2.0 w data out current (short circuit).......................50 ma *note: stresses above those listed under ?absolute maximum ratings? may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter max. unit c i1 input capacitance (a0 to a11) 5 pf c i2 input capacitance ras , cas , we , cs , cke 5pf c io output capacitance (dq) 6.5 pf c clk input capacitance (cclk, clk )4pf block diagram row decoder memory array bank 0 4096 x 256 x 16 bit column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096 x 256 x 16 bit column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096 x 256 x 16 bit column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096 x 256 x 16 bit column decoder sense amplifier & i(o) bus input buffer output buffer i/q 0 -iq 15 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a7, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we udm row addresses column addresses dll strobe gen. data strobe clk, clk clk ldm dqs
4 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S signal pin description pin type signal polarity function clk clk input pulse positive edge the system clock input. all inputs except dqs and dms are sampled on the rising edge of clk. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. dqs input/ output pulse active high active on both edges for data input and output. center aligned to input data edge aligned to output data a0 - a11 input level ? during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organization: 8m x 8 sdram can = ca8 (page length = 512 bits) in addition to the column address, a10(=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10(=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged simultaneously regardless of state of ba0 and ba1. ba0, ba1 input level ? selects which bank is to be active. dqx input/ output level ? data input/output pins operate in the same manner as on conventional drams. dm input pulse active high in write mode, dm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high. vdd, vss supply power and ground for the input buffers and the core logic. vddq vssq supply ? ? isolated power supply and ground for the output buffers to provide improved noise immunity. vref input level ? sstl reference voltage for inputs
5 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S functional description power-up sequence the following sequence is required for power up. 1. apply power and attempt to maintain cke at a low state (all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. 2. start clock and maintain stable condition for a minimum of 200us. 3. the minimum of 200us after stable power and clock (clk, clk ), apply nop & take cke high. 4. precharge all banks. 5. issue emrs to enable dll.(to issue ?dll enable? command, provide ?low? to a0, ?high? to ba0 and ?low? to all of the rest address pins, a1~a11 and ba1) 6. issue a mode register set command for ?dll rese t?. the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide ?high? to a8 and ?low? to ba0) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command to initialize device operation. note1 every ?dll enable? command resets dll. therefore sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll. extended mode register set (emrs) the extended mode register stores the data for enabling or disabling dll. the default value of the extend- ed mode register is not defined, therefore the extended mode register must be written after power up for en- abling or disabling dll. the extended mode register is written by asserting low on cs , ras, cas , we and high on ba 0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the extended mode register). the state of address pins a 0 ~ a 11 and ba 1 in the same cycle as cs , ras , cas and we low is written in the extended mode register. two clock cycles are required to complete the write operation in the extended mode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a 0 is used for dll enable or disable. ?high? on ba 0 is used for emrs. all the other address pins except a 0 and ba 0 must be set to low for proper emrs operation. a 1 is used at emrs to indicate i/o strength a 1 = 0 full strength, a 1 = 1 half strength. refer to the table for specific codes. power up sequence & auto refresh(cbr) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc min. 200 cycle ? ?? ck, ck ?? ?? ?? ?? ?? ?? emrs mrs 2 clock min. 200 s power up to 1st command dll reset 2 clock min. 6 5 4788 precharge all banks ??
6 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S mode register set (mrs) the mode register stores the data for c ontrolling t he various operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset and various vendor specific options to make ddr sdram useful for a variety of different applications. the default value of the mode register is not defined, therefore t he mode register must be written after emrs setting for proper ddr sdram operation. the mode register is written by asserting low on cs , ras , cas , we and ba 0 (the ddr sdram should be in all bank precharge with cke already high prior to writing into the mode register). the state of address pins a 0 ~ a 11 in the same cycle as cs , ras , cas , we and ba0 low is written in the mode register. two clock cycles are required to meet t mrd spec. the mode register contents can be changed using the same com- mand and clock cycle requirements during operation as long as all banks are in the idle state. the mode reg- ister is divided into various fields depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency (read latency from column address) uses a 4 ~ a 6 . a 7 is a mosel vitelic specific test mode during production test. a 8 is used for dll reset. a 7 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. 1. mrs can be issued only at all banks precharge state. 2. minimum trp is required to issue mrs command. address bus cas latency a 6 a 5 a 4 latency 0 0 0 reserve 0 0 1 reserve 01 0 2 01 1 3 1 0 0 reserve reserve 10 1 1 1 0 2.5 1 1 1 reserve burst length a 2 a 1 a 0 latency sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve a 7 mode 0 normal 1 test a 3 burst type 0 sequential 1 interleave * rfu(reserved for future use) should stay "0" during mrs cycle. a 8 dll reset 0no 1 yes mode register set 0 rfu : must be set "0" extended mode register mode register dll i/o a 0 dll enable 0 enable 1 disable a 1 i/o strength 0 full 1 half ba 0 a n ~ a 0 0 (existing)mrs cycle 1 extended funtions(emrs) command 2 01 5 34 8 67 ck, ck t ck t mrd precharge all banks mode register set t rp *2 *1 any command ba 1 ba 0 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 tm cas latency bt burst length rfu dll mrs mrs
7 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S mode register set timing burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). two par ameters define how the burst mode will operate: burst sequence and burst length. these parameters are programmable and are determined by address bits a 0 ?a 3 during the mode register set command. burst type defines the sequence in which the burst data will be delivered or stored to the sdram. two types of burst sequence are supported: sequential and interleave. the burst length controls the number of bits that will be output after a read command, or the number of bits to be input after a write command. the burst length can be programmed to values of 2, 4, or 8. see the burst length and sequence table below for programming information. burst length and sequence burst length starting length (a 2 , a 1 , a 0 ) sequential mode interleave mode 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0,1, 2, 3, 4, 5, 6, 7 0,1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5, 6 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 t5 t0 t1 t2 t3 t4 t6 t7 t8 t rp t mrd t ck pre- all mrs/emrs any m ode register set (mrs) or extended mode register set (emrs) can be issued only when all banks are in the idle state. ck, ck command i f a mrs command is issued to reset the dll, then an additional 200 clocks must occur prior to issuing any new command t9 t o allow time for the dll to lock onto the clock.
8 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S bank activate command the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the ddr sdram has four independent banks, so two bank select addresses (ba 0 and ba 1 ) are supported. the bank activate command must be applied before any read or write operation can be executed. the delay from the bank activate command to the first read or write command must meet or exceed the minimum ras to cas delay time (t rcd min). once a bank has been activated, it must be pre- charged before another bank activate command can be applied to the same bank. the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank delay time (t rrd min). bank activation timing read operation with the dll enabled, all devices operating at the same frequency within a system are ensured to have the same timing relationship between dq and dqs relative to the ck input regardless of device density, pro- cess variation, or technology generation. the data strobe signal (dqs) is driven off chip simultaneously with the output data (dq) during each read cycle. the same internal clock phase is used to drive both the output data and data strobe signal off chip to minimize skew between data strobe and output data. this internal clock phase is nominally aligned to the input differential clock (ck, ck ) by the on-chip dll. therefore, when the dll is enabled and the clock fre- quency is within the specified range for proper dll operation, the data strobe (dqs), output data (dq), and the system clock (ck) are all nominally aligned. since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed and used to latch the output data into the receiving device. the tolerance for skew between dqs and dq (t dqsq ) is tighter than that possible for ck to dq (t ac ) or dqs to ck (t dqsck ). t0 t1 t2 t3 tn tn+1 tn+2 tn+3 tn+4 tn+5 ( cas latency = 2; burst length = any) t rrd (min) t rp (min) t rc t rcd (min) begin precharge bank a ck, ck b a/address command bank/col read/a bank/row activate/a activate/b pre/a bank/row activate/a bank bank/row t ras (min)
9 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S output data (dq) and data strobe (dqs) timing relative to the clock (ck) during read cycles the minimum time during which the output data (dq) is valid is critical for the receiving device (i.e., a mem- ory controller device). this also applies to the data strobe during the read cycle since it is tightly coupled to the output data. the minimum data output valid time (t dv ) and minimum data strobe valid time (t dqsv ) are de- rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to dll jitter and power supply noise. ( cas latency = 2.5; burst length = 4 ) t0 t1 t2 t3 t4 nop nop nop d 0 ck, ck c ommand dqs dq d 2 t dqsck (max) t dqsck (min) d 1 t ac (min) t ac (max) d 3 read nop
10 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S output data and data strobe valid window for ddr read cycles read preamble and postamble operation prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe signal (dqs), must transition from hi-z to a valid logic low. the is referred to as the data strobe ?read pream- ble? (t rpre ). this transition from hi-z to logic low nominally happens one clock cycle prior to the first edge of valid data. once the burst of read data is concluded and given that no subsequent burst read operations are initiated, the data strobe signal (dqs) transitions from a logic low level back to hi-z. this is referred to as the data strobe ?read postamble? (t rpst ). this transition happens nominally one-half clock period after the last edge of valid data. consecutive or ?gapless? burst r ead operations are possible from the same ddr sdram device with no requirement for a data strobe ?read? preamble or postamble in between the groups of burst data. the data strobe read preamble is required before the ddr device drives the first output data off chip. similarly, the data strobe postamble is initiated when the device stops driving dq data at the termination of read burst cy- cles. d 0 d 1 ( cas latency = 2; burst length = 2) t0 t1 t2 t3 t4 read nop nop nop c ommand dqs dq t dv (min) ck, ck t dqsv (min)
11 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S data strobe preamble and postamble timings for ddr read cycles consecutive burst read operation and effects on the data strobe preamble and postamble ( cas latency = 2; burst length = 2) t0 t1 t2 t3 t4 read nop nop nop d 0 d 1 ck, ck c ommand dqs dq t rpre (max) t rpst (min) t rpre (min) t rpst (max) t dqsq (max) t dqsq (min) nop read b nop nop nop nop read a d0 a d1 a nop d2 a d3 a command dqs dq burst read operation (cas latency = 2; burst length = 4) ck, ck nop d0 b d1 b d2 b d3 b nop read b nop nop nop nop read a d0 a d1 a nop d2 a d3 a command dqs dq burst read operation ( cas latency = 2; burst length = 4) ck, ck nop d0 b d1 b d2 b d3 b
12 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S auto precharge operation the auto precharge operation can be issued by having column address a 10 high when a read or write command is issued. if a 10 is low when a read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. when the auto precharge command is activated, the active bank automatically begins to precharge at the earliest possible moment during the read or write cycle once t ras (min) is satisfied. read with auto precharge if a read with auto precharge command is initiated, the ddr sdram will enter the precharge operation n-clock cycles measured from the last data of the burst read cycle where n is equal to the cas latency pro- grammed into the device. once the autoprecharge operation has begun, the bank cannot be reactivated until the minimum precharge time (t rp ) has been satisfied. read with autoprecharge timing ( cas latency = 2; burst length = 4 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 begin autoprecharge nop ba r w/ap nop nop nop nop nop ba ck, ck c ommand dqs dq t ras (min) t rp (min) earliest bank a reactiva te t9
13 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S read with autoprecharge timing as a function of cas latency t0 t1 t2 t3 t4 t5 t6 t7 t8 begin autoprecharge nop rap nop nop nop nop ba nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq dqs dq cas latency=2 cas latency=2.5 cas latency=3 ( cas latency = 2, 2.5, 3; burst length = 4) d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3
14 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S precharge timing during read operation for the earliest possible precharge command without interrupting a read burst, the precharge command may be issued on the rising clock edge which is cas latency (cl) clock cycles before the end of the read burst. a new bank activate (ba) command may be issued to the same bank after the ras precharge time (t rp ). a precharge command can not be issued until t ras (min) is satisfied. read with precharge timing as a function of cas latency t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop read nop nop pre a nop ba nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 cas latency=3 ( cas latency = 2, 2.5, 3; burst length = 4)
15 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S burst stop command the burst stop command is valid only during burst read cycles and is initiated by having ras and cas high with cs and we low at the rising edge of the clock. when the burst stop command is issued during a burst read cycle, both the output data (dq) and data strobe (dqs) go to a high impedance state after a delay (l bst ) equal to the cas latency programmed into the device. if the burst stop command is issued during a burst write cycle, the command wi ll be treated as a nop command. read terminated by burst stop command timing ( cas latency = 2, 2.5, 3; burst length = 4) t0 t1 t2 t3 t4 t5 t6 bst nop nop nop nop read d 0 d 1 ck, ck command dqs dq d 0 d 1 dqs dq d 0 d 1 dqs dq c as latency = 2 c as latency = 2.5 c as latency = 3 l bst l bst l bst
16 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S read interrupted by a precharge a burst read operation can be interrupted by a precharge of the same bank. the precharge command to output disable latency is equivalent to the cas latency. read interrupted by a precharge timing burst write operation the burst write command is issued by having cs , cas , and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column address. the memory controller is re- quired to provide an input data strobe (dqs) to the ddr sdram to strobe or latch the input data (dq) and data mask (dm) into the device. during write cycles, the data strobe applied to the ddr sdram is required to be nominally centered within the data (dq) and data mask (dm) valid windows. the data strobe must be driven high nominally one clock after the write command has been registered. timing parameters t dqss (min) and t dqss (max) define the allowable window when the data strobe must be driven high. input data for the first burst write cycle must be applied one clock cycle after the write command is regis- tered into the device (wl=1). the input data valid window is nominally centered around the midpoint of the data strobe signal. the data window is defined by dq to dqs setup time (t qdqss ) and dq to dqs hold time (t qdqsh ). all data inputs must be supplied on each rising and falling edge of the data strobe until the burst length is completed. when the burst has finished, any additional data supplied to the dq pins will be ignored. write preamble and postamble operation prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe signal (dqs), must transition from hi-z to a valid logic low. this is referred to as the data strobe ?write preamble?. this transition from hi-z to logic low nominally happens on the falling edge of the clock after the write com- mand has been registered by the device. the preamble is explicitly defined by a setup time (t wpres (min)) and hold time (t wpreh (min)) referenced to the first falling edge of ck after the write command. t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop read nop nop pre a nop ba nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 d 0 d 1 d 2 d 3 dqs dq d 0 d 1 d 2 d 3 dqs dq cas latency=2 cas latency=2.5 cas latency=3 ( cas latency = 2, 2.5, 3; burst length = 8)
17 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S burst write timing once the burst of write data is concluded and given that no subsequent burst write operations are initiated, the data strobe signal (dqs) transitions from a logic low level back to hi-z. this is referred to as the data strobe ?write postamble?. this transition happens nominally one-half clock period after the last data of the burst cycle is latched into the device. ( cas latency = any; burst length = 4 ) t0 t1 t2 t3 t4 write nop nop nop d 0 d 1 d 2 d 3 ck, ck command d qs(nom) dq(nom) t wpres t wpreh t dqss t wpst t qdqsh d 0 d 1 d 2 d 3 dqs(min) dq(min) t dqss (min) d 0 d 1 d 2 d 3 dqs(max) dq(max) t wpres (min) t dqss (max) t qdqss t qdqss t qdqsh t wpreh (min) t wpreh (max) t wpres (max)
18 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S write interrupted by a precharge a burst write can be interrupted before completion of the burst by a precharge command, with the only restriction being that the interval that separ ates the commands be at least one clock cycle. write interrupted by a precharge timing write with auto precharge if a 10 is high when a write command is issued, the write with auto precharge function is performed. any new command to the same bank should not be issued until the internal precharge is completed. the internal precharge begins after keeping t wr (min.). write with auto precharge timing ( cas latency = 2; burst length = 8) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 write a nop pre a nop nop nop nop nop nop nop nop ck, ck c ommand dqs t12 dm d 0 d 1 d 2 d 3 dq data is masked by precharge command data is masked by dm input dqs input ignored d 4 d 5 t wr ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop wap nop nop nop nop nop nop ba ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 t1 0 t wr (min) begin autoprecharge
19 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S precharge timing during write operation precharge timing for write operations in drams requires enough time to satisfy the write recovery require- ment. this is the time required by a dram sense amp to fully store the voltage level. for ddr sdrams, a timing parameter (t wr ) is used to indicate the required amount of time between the last valid write operation and a precharge command to the same bank. the ?write recovery? operation begins on the rising clock edge after the last dqs edge that is used to strobe in the last valid write data. ?write recovery? is complete on the next rising clock edge that is used to strobe in the precharge command. for the earliest possible precharge command following a write burst without interrupting the burst, the minimum time for ?write recovery? is 1.25 clock cycles. maximum ?write recovery? time is 1.75 clock cycles. write with precharge timing ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 nop write nop nop nop nop pre a nop ck, ck c ommand dqs dq t ras (min) t rp (min) ba nop t9 t1 0 t wr (min) d 0 d 1 d 2 d 3 dqs dq t wr (max) ba
20 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S data mask function the ddr sdram has a data mask functi on that is used in co njunction with the writ e cycle, but not the read cycle. when the data mask is activated (dm high) during a write operation, the write is blocked (mask to data latency = 0). when issued, the data mask must be referenced to both the rising and falling edges of data strobe. data mask timing burst interruption read interrupted by a read a burst read can be interrupted before completion of the burst by issuing a new read command to any bank. when the previous burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. the data from the first read command continues to appear on the outputs until the cas latency from the interrupting read command is satisfied. at this point, the data from the interrupting read command appears on the bus. read commands can be issued on each rising edge of the system clock. it is illegal to interrupt a read with autoprecharge command with a read command. read interrupted by a read command timing ( cas latency = any; burst length = 8) t0 t1 t2 t3 t4 t5 t6 t7 t8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 nop nop nop nop nop nop nop write ck, ck c ommand dqs dq dm t9 t dmdqss t dmdqss t dmdqsh t dmdqsh ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 read b nop nop nop nop nop nop da0 da1 db0 db1 read a db2 db3 ck, ck c ommand dqs dq t9
21 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S read interrupted by a write to interrupt a burst read with a write command, a burst stop command must be asserted to stop the burst read operation and 3-state the dq bus. additionally, control of the dqs bus must be turned around to allow the memory controller to drive the data strobe signal (dqs) into the ddr sdram for the write cycles. once the burst stop command has been issued, a write command can not be issued until a minimum delay or latency (l bst ) has been satisfied. this latency is measured from the burst stop command and is equivalent to the cas latency programmed into the mode register. in instances where cas latency is measured in half clock cycles, the minimum delay (l bst ) is rounded up to the next full cl ock cycle (i.e., if cl=2 then l bst =2, if cl=2.5 then l bst =3). it is illegal to interrupt a read wi th autoprecharge command with a write command. read interrupted by burst stop command followed by a write command timing write interrupted by a write a burst write can be interrupted before completion by a new write command to any bank. when the pre- vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new address. the data from the first write command continues to be input into the device until the write latency of the interrupting write command is satisfied (wl=1) at this point, the data from the interrupting write com- mand is input into the device. write commands can be issued on each rising edge of the system clock. it is illegal to interrupt a write with autoprecharge command with a write command. write interrupted by a write command timing ( cas latency = 2; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 bst nop write nop nop nop nop d 0 d 1 read d 0 d 1 d 2 d 3 ck, ck c ommand dqs dq t9 l bst ( cas latency = any; burst length = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 write a nop nop write b nop nop nop nop da0 da1 db0 db1 db2 db3 ck, ck c ommand dqs dq dm t9 write latency dm0 dm1 dm0 dm1 dm2 dm3
22 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S write interrupted by a read a burst write can be interrupted by a read command to any bank. if a burst write operation is interrupted prior to the end of the burst operation, then the last two pieces of input data prior to the read command must be masked off with the data mask (dm) input pin to prevent invalid data from being written into the memory array. any data that is present on the dq pins coincident with or following the read command will be masked off by the read command and will not be written to the array. the memory controller must give up control of both the dq bus and the dqs bus at least one clo ck cycle before the read dat a appears on the outputs in order to avoid contention. in order to avoid data contention within the device, a delay is required (t cdlr ) from the last valid data input before a read command can be issued to the device. it is illegal to interrupt a write with autoprecharge command with a read command. write interrupted by a read command timing auto refresh the auto refresh command is issued by having cs , ras , and cas held low with cke and we high at the rising edge of the clock. all banks must be precharged and idle for a t rp (min) before the auto refresh com- mand is applied. no control of the address pins is required once this cycle has started because of the internal address counter. when the auto refresh cycle has completed, all banks will be in the idle state. a delay be- tween the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t rfc (min). commands may not be issued to the device once an auto refresh cycle has begun. cs input must remain high during the refresh period or nop commands must be registered on each rising edge of the ck input until the refresh period is satisfied. auto refresh timing ( cas latency = 2; burst length = 8 ) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 write nop read nop nop nop nop nop nop nop nop ck, ck c ommand dqs t12 dm d 2 d 3 d 4 d 5 d 0 d 2 d 3 d 4 d 5 d 6 d 1 d 7 dq data is masked by read command data is masked by dm input dqs input ignored d 0 d 1 t cdlr t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 nop ck, ck c ommand cke t11 auto ref any high pre all t rfc t rp
23 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S self refresh a self refresh command is defined by having cs , ras , cas and cke held low with we high at the rising edge of the clock (ck). once the self refresh command is initiated, cke must be held low to keep the device in self refresh mode. during the self refresh operation, all inputs except cke are ignored. the clock is inter- nally disabled during self refresh operation to reduce power consumption. the self refresh is exited by sup- plying stable clock input before returning cke high, asserting deselect or nop command and then asserting cke high for longer than t srex for locking of dll. the auto refresh is required before self refresh entry and after self refresh exit. power down mode the power down mode is entered when cke is low and exited when cke is high. once the power down mode is initiated, all of the receiver circuits except clock, cke and dll circuit tree are gated off to reduce power consumption. all banks should be in idle state prior to entering the precharge power down mode and cke should be set high at least 1tck+tis prior to row active command. during power down mode, refresh operations cannot be performed, therefore the dev ice cannot remain in power down mode longer than the refresh period (t ref ) of the device. command cke stable clock t srex auto refresh nop self refresh ck, ck cke precharge active read nop active power down power down exit active entry power exit down power entry down precharge precharge command ck, ck
24 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S sstl_2 input ac/dc logic levels note: 1. the relationship of the v ddq of the driving device and the v ref of the receiving device is what determines noise margins. however, in the case of v ih (max) (input overdrive), it is the v ddq of the receiving device that is referenced. in the case where a device is implemented such that supports sstl_2 inputs but has no sstl_2 outputs (e.g., a translator), and therefore no v ddq supply voltage connection, inputs must tolerate input overdrive to 3.0v (high corner v ddq +300mv.) sstl_2 ac test conditions notes: 1. input waveform timing is referenced to the input signal crossing the v ref level applied to the device. 2. compliant devices must still meet the v ih (ac) and v il (ac) specifications under actual use conditions. 3. the 1 v/ns input signal minimum slew rate is to be maintained in the v il max (ac) to v il min (ac) range of the input signal swing. sstl_2 output buffers the input voltage provided to the receiver depends on three parameters: v ddq and current driv e capabilities of t he output buffer termination voltage termination resistance v ddq =2.5 + 0.2v class ii sstl_2 output buffer (driver) symbol parameter min max units notes v ih (dc) dc input logic high v ref +0.18 v ddq +0.3 v 1 v ih (ac) ac input logic high v ref +0.35 ? v v il (dc) dc input logic low ?0.30 v ref ?0.18 v v il (ac) ac input logic low ? v ref ?0.35 v symbol parameter value units notes v ref input reference voltage 0.5*v ddq v1 v swing (max) input signal maximum peak to peak swing 1.5 v 1, 2 slew input signal minimum slew rate 1.0 v/ns 3 v ref v in v tt = 0.5 *v ddq c load = 30pf v ddq v ssq v out receiver rt=50 ? output buffer
25 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S dc characteristics recommended operating conditions unless otherwise noted, t a =0 to 70c parameter symbol test condition cas latency version unit -36 ?4 ?5 operating current (one bank active) i cc 1 burst length=2 t rc =t rc (min) i ol =0ma 155 150 140 ma precharge standby current in power-down mode i cc2 p cke=v il (max), t cc =10ns 20 ma precharge standby current in non power-down mode i cc2 n cke=vih(min), cs=vih(min), tcc=10ns input signals are changed once during 20ns 45 ma active standby current in power-down mode i cc3 p cke=v il (max), t cc =10ns 30 ma active standby current in non- power-down mode i cc3 n cke=vih(min), cs=vih(min), tcc=10ns input signals are changed once during 20ns 60 ma operating current (burst mode) i cc4 i ol =0ma page burst all banks activated t ccd =2cks 2 165 160 150 ma refresh current i cc5 t rc =t rfc (min) 200 ma self refresh current i cc6 cke=0.2v 2 ma
26 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S ac characteristics (t a =0 to +70c, v cc =3.3 0.3v) symbol parameter -36 ?4 ?5 unit min. max. min. max. min. max. clock cycle t ck clock cycle cl = 2.0 5.4 15 6 15 7.5 15 ns cl = 2.5 4.3 15 4.8 15 6 15 ns cl = 3.0 3.6 15 4 15 5 15 ns t ch clock duty cycle 0.45 0.55 0.45 0.55 0.45 0.55 % t cl 0.45 0.55 0.45 0.55 0.45 0.55 % command cycle t ras row active time (act->pre) 40 100k 40 100k 40 100k ns t rp row precharge (pre->act) 18 - 18 - 18 - ns t rc row cycle (act->act) 60 - 60 - 60 - ns t rcd ras->cas delay (act->wr/rd) 18 - 18 - 20 - ns t rrd ras->ras delay (acta->actb) 8 - 8 - 10 - ns t rfc auto-refresh (ref->ref/act) 68 - 68 - 70 - ns t ref refresh cycle - 64 - 64 - 64 ms t srex(dll) self-refresh exit delay 200 - 200 - 200 - cycles t srex 1-1-1-t rc t is cmd, addr->clk setup 0.9 - 0.9 - 1.0 - ns t ih cmd, addr->clk hold 0.9 - 0.9 - 1.0 - ns t ccd cas->cas delay (cola->colb) 1 1 1 t ck t mrd mode register set delay 2 2 2 t ck t pdent power down entry delay 1 1 1 t ck t pdex(dll) power down exit delay 1 1 1 t ck t pdex 111t ck read cycle t ac clk->dq skew -0.1 0.1 -0.1 0.1 -0.1 0.1 t ck t dqsck clk->dqs skew -0.1 0.1 -0.1 0.1 -0.1 0.1 t ck t dqsq dqs->dq skew -0.075 0.075 -0.075 0.075 -0.075 0.075 t ck t dv dq/dqs valid window 0.3 - 0.3 - 0.3 - t ck t rpre read dqs preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck t rpst read dqs postamble 0.4 0.6 0.4 0.6 0.4 0.6 t ck
27 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S write cycle t wpres write preamble dqs setup 0 0.5 0 0.5 0 0.5 t ck t wpreh write preamble dqs hold 0.25 1.25 0.25 1.25 0.25 1.25 t ck t dqss write preamble clk->dqs (first) 0.75 1.25 0.75 1.25 0.75 1.25 t ck t dsh write dqs high width 0.4 0.6 0.4 0.6 0.4 0.6 t ck t dsl write dqs low width 0.4 0.6 0.4 0.6 0.4 0.6 t ck t wpst write postamble dqs (last) -> hi-z 0.4 0.6 0.4 0.6 0.4 0.6 t ck t dqsr write (last din) -> read command 1.25 1.75 1.25 1.75 1.25 1.75 t ck t wr write (last din) -> pre command 1.25 1.75 1.25 1.75 1.25 1.75 t ck t ds dq/dm -> dqs setup (data setup) 0.075 - 0.075 - 0.075 - t ck t dh dq/dm -> dqs hold (data hold) 0.075 - 0.075 - 0.075 - t ck t qdqss date input to data strobe setup time 0.075 - 0.075 - 0.075 - t ck t qdqsh date input to data strobe hold time 0.075 - 0.075 - 0.075 - t ck t dmdsqs date mask to data strobe setup time 0.075 - 0.075 - 0.075 - t ck t dmdqsh date mask to data strobe hold time 0.075 - 0.075 - 0.075 - t ck ac characteristics (continued) (t a =0 to +70c, v cc =3.3 0.3v) symbol parameter -36 ?4 ?5 unit min. max. min. max. min. max.
28 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S complete list of operation commands ddr sdram function truth table current state 1 cs ras cas we bs addr action idle h l l l l l l l x h h h l l l l x h h l h h l l x h l x h l h l x x bs bs bs bs x op- x x x x ra ap x code nop or power down nop illegal 2 illegal 2 row (&bank) active; latch row address nop 4 auto-refresh or self-refresh 5 mode reg. access 5 row active h l l l l l l x h h h l l l x h l l h h l x x h l h l x x x bs bs bs bs x x x ca,ap ca,ap x ap x nop nop begin read; latch ca; determineap begin write; latch ca; determineap illegal 2 precharge illegal read h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs bs bs bs x x x x ca,ap ca,ap x ap x nop (continue burst to end;>row active) nop (continue burst to end;>row active) term burst term burst, new read, determineap 3 illegal (need term burst before write) illegal to same bank, other bank 0k if trrd is satisfied term burst, precharge illegal write h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs bs bs bs x x x x ca,ap ca,ap x ap x nop (continue burst to end;>row active) nop (continue burst to end;>row active) nop term burst, start read, determineap 3 term burst, new write, determineap 3 illegal 2 term burst, precharge 3 illegal read with auto precharge h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs x bs bs x x x x x x x ap x nop (continue burst to end;> precharge) nop (continue burst to end;> precharge) illegal 2 illegal 2 illegal illegal 2 illegal 2 illegal
29 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S ddr sdram function truth table (continued) current state 1 cs ras cas we bs addr action write with auto precharge h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs x bs bs x x x x x x x ap x nop (continue burst to end;> precharge) nop (continue burst to end;> precharge) illegal 2 illegal 2 illegal illegal 2 illegal 2 illegal precharging h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop;> idle after trp nop;> idle after trp nop illegal 2 (0k provided trp satisfied) act nop 4 illegal row activating h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop;> row active after trcd nop;> row active after trcd illegal 2 (0k if trcd satisfied) read/write (0k to other bank if trrd satisfied) act precharge illegal write recovering h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop nop illegal 2 illegal 2 illegal 2 illegal 2 illegal refreshing h l l l l x h h l l x h l h l x x x x x x x x x x x x x x x nop;> idle after trc nop;> idle after trc illegal illegal illegal mode register accessing h l l l l x h h h l x h h l x x h l x x x x x x x x x x x x nop nop illegal illegal illegal
30 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S clock enable (cke) truth table abbreviations: ra = row address bs = bank select address ca = column address ap = auto precharge notes for sdram function truth table: 1. current state is state of the bank determined by bs. all entries assume that cke was active (high) during the preceding clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by bs, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. the precharge bank(s) indicated by bs and ap. 5. illegal if any bank is not idle. 6. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 7. power-down and self-refresh can be entered only from the all banks idle state. 8. must be legal command as defined in the sdram function truth table. state(n) cke n-1 cke ncs ras cas we addr action self-refresh 6 h l l l l l l x h h h h h l x h l l l l x x x h h h l x x x h h l x x x x h l x x x x x x x x x x invalid exit self-refresh, idle after trc exit self-refresh, idle after trc illegal illegal illegal nop (maintain self-refresh) power-down h l l l l l l x h h h h h l x h l l l l x x x h h h l x x x h h l x x x x h l x x x x x x x x x x invalid exit power-down, > idle. exit power-down, > idle. illegal illegal illegal nop (maintain low-power mode) all. banks idle 7 h h h h h h h h l h l l l l l l l l x h l l l l l l x x x h h h l l l x x x h h l h l l x x x h l x x h l x x x x x x x x x x refer to the function truth table enter power- down enter power- down illegal illegal illegal enter self-refresh illegal nop any state other than listed above h h l l h l h l x x x x x x x x x x x x x x x x x x x x refer to the function truth table begin clock suspend next cycle 8 exit clock suspend next cycle 8 . maintain clock suspend.
31 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S multibank interleaving read t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t rrd t multibank interleaving read ( cas latency = 2; burst length = 4) high baa bab act a act b baa bab ra rb ca cb qa0 qa1 qa2 qa3 rd a rd b ra rb ra rb qb0 qb2 qb3 qb1 clk clk cke cs ras cas we ba0, ba1 a11 a10, ap a0-a9 dqs dq dm c ommand rcdb t rcda t
32 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S read interrupted by a read t0 t1 t2 t3 t4 t5 t6 t7 t8 t ccd high baa rd a ca cb qa0 qa1 read interrupted by a read ( cas latency = 2; burst length = 8) bab qb0 qb1 qb2 qb3 qb4 qb5 qb6 qb7 rd b clk clk cke cs ras cas we ba0, ba1 a11 a10, ap a0-a9 dqs dq dm c ommand
33 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S multi bank interleaving write (@ bl = 4) t0 t1 t2 t3 t4 t5 t6 t7 t8 t rcd t rrd t t high baa bab act a baa bab ra rb ca cb da0 da1 da2 da3 db0 db1 db2 db3 act b wr a wr b ra rb clk clk cke cs ras cas we ba0, ba1 a11 ba a10, ap a ddr (a0~a9, a11) dqs dq dm command rcdb t
34 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S auto precharge after read burst (@ bl = 8, cl = 2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp t high ba auto precharge start qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 rap ra ba ra ra ck ck cke cs ras cas we ba0, ba1 a11 a10, ap a0-a9 dqs dq dm c ommand ca ba
35 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S auto precharge after write burst (@ bl=8) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t rp t high baa wr baa ca ra da0 da1 da2 da3 da4 da5 da6 da7 ba auto precharge start auto precharge after write burst (burst length = 8) ra ra ck ck cke cs ras cas we ba0, ba1 a11 a10, ap a0-a9 dqs dq dm c ommand wpst t wr t +
36 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S read interrupted by precharge (@bl = 8, cl = 2) t0 ck ck cs we a11 dqs dq dm c ommand ba0, ba1 a10, ap a0?a9 ras cas cke high t1 t2 t3 t4 baa baa ca qa0 qa1 qa2 pre rd qa3 qa4 qa5 t5 t6 t7
37 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S write interrupted by a read (@bl=8, cl=2) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t cdlr high baa wr bab ca cb da0 da1 da2 da3 da4 da5 rd qb0 qb1 qb2 qb3 qb4 qb5 qb6 write interrupted by a read ( cas latency = 2; burst length = 8) qb7 da6 da7 ck ck cke cs ras cas we ba0, ba1 a11 a10, ap a0-a9 dqs dq dm c ommand
38 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S write burst t0 t1 t2 t3 t4 t5 t6 t wr high baa wr baa ca da0 da1 da2 da3 pre write burst (burst length = 4 ) clk clk cke cs ras cas we ba0, ba1 a11 a10, ap a0-a9 dqs dq dm c ommand
39 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S read interrupted by a write and burst stop t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 high rd qa0 qa1 qb0 qb1 qb2 qb3 qb4 qb5 qb6 qb7 wr bst ca cb baa bab clk clk cke cs ras cas we (ba0, ba1) a11 ba a10, ap a ddr (a0-a9, a11) dqs dq dm command dqss t lbst
40 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S data mask function (@bl=8) only for write t0 t1 t2 t3 t4 t5 t6 high baa wr ca da0 da1 data mask function during burst write cycles ( cas latency = 2; burst length = 8) da2 da3 da4 da5 da6 da7 ck cke cs ras cas we ba0, ba1 a11 a10, ap a0-a9 dqs dq dm c ommand ck
41 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S power up sequence and auto refresh (cbr) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 200 clock min 200 s min t rc power up sequence and auto refresh (cbr) hi-z hi-z high level is required minimum of two refresh cycles is required two clock minimum ---dll reset ---dll enable ---precharge all ---any command ---mode register set clk clk cke cs ras cas we ba0 ba1 a0 a1-a6 a7 a8 a9, a11 a10 dq dm dqs precharge all
42 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S mode register/extended mode register set t0 t1 t2 t3 t4 t5 t6 t7 t rp t ck high mode register set extended mode register set hi-z hi-z ---precharge command all banks ---mode register set command ---any command two clock minimum adrskey ---extended mode register set command clk clk cke cs ras cas we b a0, ba1 a9, a11 a10 a0-a8 dq dm dqs
43 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S package diagram 66-pin tsop-ii (400 mil) units : millimeters 0.30 0.08 0.65typ (0.71) 22.22 0.10 0.125 (0.80) 10.16 0.10 0 ~8 #1 #33 #66 #34 (1.50) (1.50) 0.65 0.08 1.00 0.10 1.20max (0.50) (0.50) (10.76) 11.76 0.20 (10 ) (10) +0.075 -0.035 (0.80) 0.10 max 0.075 max [] 0.05 min (10 ) (10 ) ( r 0 . 1 5 ) 0.210 0.05 0.665 0.05 ( r0. 1 5) ( 4 ) ( r 0 . 2 5 ) ( r 0 .2 5 ) 0.45~0.75 0.25typ note 1. ( ) is reference
44 V58C365164S rev. 1.7 march 2002 mosel vitelic V58C365164S worldwide offices ? copyright , mosel vitelic corp. printed in u.s.a. the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality contr ol sampling techniques which are intended to provide an assuranc e of high quality products suitable for usual commercial applica - tions. mosel vitelic does not do testing appropriate to provid e 100% product quality assurance and does not assume any liab il- ity for consequential or incidental arising from any use of its prod - ucts. if such products are to be used in applications in whic h personal injury might occur from failure, purchaser must do i ts own quality assurance testing appropriate to such applications. u.s. sales offices u .s.a. 3 910 north first street s an jose, ca 95134 p hone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 w est 3 910 north first street s an jose, ca 95134 p hone: 408-433-6000 fax: 408-433-0952 central / east 604 fieldwood circle richardson, tx 75081 phone: 214-352-3775 fax: 214-904-9029

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